Memory devices frequently include bitcells arrayed in a matrix of rows and columns. Each bitcell stores a bit, the value of which depends upon the state of the bitcell. Thus, a bitcell typically has at least two bit value storage states in which in one bit value storage state, the bitcell state represents a logical 0 bit, and another bit value storage state which represents a logical 1 bit.
One or more bitcells of memory may fail to properly retain their bit value storage states due to various factors. In dynamic random access memory (DRAM), one such factor is a failure mechanism often referred to as “Row-hammer” (RH) in which bitcells may inadvertently change state due to accessing an adjacent row of bitcells repeatedly. For example, repeated access to one row, often referred to as the “attacker row” may cause bitcells in an adjacent row, often referred to as the “not-accessed” or “victim” row, to change bit value storage states due to the repetitive access to the attacker row. This row-hammer failure mechanism may be a problem both in terms of reliability degradation due to undetected data corruption, as well as security vulnerability should a malicious user purposefully flip bits in a victim row to gain unauthorized access to a restricted area of memory.
Spin Transfer Torque Random Access Memory (STTRAM) is a type of magnetoresistive Random Access Memory (MRAM) which is non-volatile and is typically used for memory circuits, such as, cache, memory, secondary storage, and other memory applications. The bitcells of STTRAM memory may be smaller and have greater durability as compared to the bitcells of other types of memory. Hence, STTRAM may be particularly suitable for on-die memory such as memory for a processor, and also off-die memories such as DRAM and non-volatile memories, such as Flash memory, and other applications. For example, STTRAM may be used to replace on-die memories such as Static Random Access Memory (SRAM) and embedded or enhanced Dynamic Random Access Memory (eDRAM). STTRAM memory also may often be operated at reduced power levels and may be less expensive as compared to other memory types.